In most digital processing systems, such as microprocessor-based computer systems, the main or primary memory is a DRAM. The term “DRAM” is an acronym for “Dynamic Random Access Memory”. “Dynamic” indicates that for the memory to remember data, the memory requires every bit to be refreshed within a certain time period. As is well known, data is stored capacitively in a DRAM and hence data must be regenerated regularly to avoid data losses due to capacitive leakage. When the power is removed from the DRAM, the data is lost. “Random Access” indicates that each cell in the memory can be read or written in any order. This contrasts a sequential memory device where data must be read or written in a certain order. The reason behind the popularity of DRAMs for high-capacity memories in digital processing systems is the low cost per bit due to the high memory density.
The memory cells of a DRAM are arranged in rows and columns, and a given memory cell in the DRAM is accessed by first applying a row address and then applying a column address to the DRAM. The row address is strobed into the DRAM by activating a row address strobe (RAS) signal, thus energizing the selected row. The column address is strobed into the DRAM by activating a column address strobe (CAS) signal, and data is selected from the specified column in the energized row. In general, the DRAM address is multiplexed into the DRAM such that the same terminals are used, at different times, for the row address and the column address.
Access to the DRAM is normally controlled by a DRAM controller that generates the necessary control and address signals to the DRAM and determines the sequence and relative timing of these signals.
In general, processor cores are designed to suit simple memories, such as static random access memories (SRAMs), sometimes used as cache memories. Traditionally, the processor-memory interface is designed in such a way that, for each memory access, the processor has to decide whether a read or write operation is to be executed, and also has to determine a complete memory address to be used before initiating the read of write access to the memory. For a DRAM, which is a rather complex memory with a multiplexed addressing procedure, this generally means that the DRAM will be relatively slow with long access times. In this respect, DRAMs are often considered as the bottlenecks of digital processing systems.
A common way of alleviating this problem is to use a small but fast cache memory as a buffer between the processor and the larger and slower DRAM. The cache memory includes copies of small parts of data and/or program information stored in the DRAM. When the processor has to read a memory cell not available in the cache memory, that cell will be copied together with a number of adjacent cells from the DRAM to the cache memory. For subsequent accesses to these cells, the processor then interfaces the fast cache memory instead of the DRAM.
In addition to the processor-memory interface, peripheral input/output devices also need to communicate with the primary memory, which often is a DRAM. For this purpose it is normal practice to use a standard technique called direct memory access (DMA). DMA is generally a technique devised to allow peripheral devices to communicate with the primary memory without significantly involving the processor. The processor merely initializes a DMA controller to take or receive a determined number of bytes from or to the primary memory starting at a predetermined location. The processor then suspends any task that cannot resume until the DMA transfer is completed, and gets on with the next highest priority task. Upon completion of the DMA transfer, the DMA controller informs the computer that the DMA transfer is complete. In response, the processor suspends the current task and resumes the task that originally requested the DMA. If the resumed task is now complete, the suspended task or a higher priority task may be resumed.